`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/29 16:22:01
// Design Name: 
// Module Name: stall
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module stall(
    input wire rst,
    input wire req_ex,
    input wire req_id,
    output reg[`STALL_BUS]  stall_res
    );
    always @(*) begin
        if(rst == `ResetEnable) begin
            stall_res <= `ZeroWord;
        end else if(req_ex == 1'b1) begin
            stall_res <= 6'b001111;
        end else if(req_id == 1'b1) begin
            stall_res <= 6'b000111;
        end else begin
            stall_res <= 6'b000000;
        end
    end
    
endmodule
